1. Field of Invention
The present invention relates generally to the field of data networking and electronic component interface. More particularly, the present invention is directed in one exemplary aspect to protecting serial bus ports from transient damage.
2. Description of Related Technology
A number of different data bus and port technologies are known in the prior art. These include, for example, the well known USB (universal serial bus) and IEEE-Std-1394 or “Firewire”, as well as peripheral component interface (PCI) and RS-232, which may be used in electronic devices such as personal computers, consumer goods (e.g., DSTBs, cameras, printers), and the like.
The interconnection of one device to another via a data port can produce certain undesired side-effects. For example, when serial bus interface devices are “hot” plugged (or unplugged) to a serial bus port, the serial bus transceiver (e.g., PHY) may be damaged when high-current external devices are used. This is because an intermittent connection on the DC power return connection causes the signal pins to carry the external device current, which raises the signal voltage above that of the power rails, exceeding the PHY device ratings and causing PHY degradation or destruction. In this exemplary context, the presence of excessive voltage on the signal pins due to intermittent connection on the DC power return is often referred to as a “late-VG” event.
One current approach to transient protection employs a Zener diode to protect against late-VG events by bleeding excessive voltages on the signal pairs to ground. With a suitable choice of diode, based at a suitable level, this approach reduces the incidence of failures seen in the field by a significant amount (typically on the order of 50%). However, highly stressful late-VG events cause failure of either the Zener diode or the PHY chip (or both). Typically, the Zener fails “shorted” or in a low resistance state, effectively shorting the signal rails to ground and preventing proper serial bus operation.
One approach to addressing the foregoing issue involves using a circuit to detect a high return voltage on the signal pairs by comparing this voltage with a preset voltage level. The circuit responds to this condition by turning off the outgoing port power.
However, the aforementioned approach has a variety of shortcomings. First, the response time of the circuit is often far too slow; damage may well be caused before the port power is turned off and consequently return power is abated.
Second, the Zener diode commonly used in this circuit has also proved in practice to be susceptible to the same failure cause.
Third, once the power is turned off, the circuit fails to turn power back on after an intended (e.g., half-second) delay.
Fourth, even with a sufficiently fast circuit response time, a comparatively high voltage can be seen in the case of shorts or near-shorts between outgoing power terminals and the signal pairs.
Prior art circuitry and methods only loosely concern themselves with these issues. For example, U.S. Pat. No. 5,077,675 to Tam issued Dec. 31, 1991 entitled “Power-on-concurrent maintenance” discloses a power sequencer for connecting a system to an electrical power supply without powering down the system and without damage to the system or the power supply. A plurality of sequentially engageable contacts are coupled to the power supply for receiving power signals. The contacts are spatially positioned to toggle in a predetermined sequence during engagement. A controller is coupled to the contacts, for supplying a terminal signal to the load in response to the predetermined sequence of toggling of the contacts and in response to the power signals. The controller has a control circuit for generating a control signal which varies in response to the sequence, and a regulator, coupled to the control circuit, for regulating the terminal signal in response to the control signal.
U.S. Pat. No. 5,079,455 to McCafferty, et al. issued Jan. 7, 1992 entitled “Surge current-limiting circuit for a large-capacitance load” discloses a circuit for limiting switch-on surge current to a load including a large capacitance includes a MOSFET whose controlled path is connected in series with the capacitance across power supply terminals. A resistor and a capacitor, having a relatively small capacitance, are also connected in series with the controlled path, and a junction between the resistor and capacitor is connected to a gate of the MOSFET via a further resistor to provide a negative feedback path for charging the load capacitance with a constant current when power is applied. A further capacitor prevents initial turn-on of the MOSFET, and a Zener diode limits the gate voltage. An alternative arrangement using a differential amplifier is described. The resistive part of the load can be connected in parallel with the load capacitance, or to the power supply terminals for which it can be separately switched in dependence upon the gate voltage.
U.S. Pat. No. 5,428,523 to McDonnal issued Jun. 27, 1995 entitled “Current sharing signal coupling/decoupling circuit for power converter systems” discloses an improved current sharing signal coupling/decoupling circuit for power converter systems, including the provision of an individual current sharing signal coupling/decoupling circuit for each module of a number of parallel connected modules, each circuit providing an interface between a module's “current sharing signal” port and a common connection bus. The signal coupling/decoupling circuits also share a common ground noted in the disclosure as “current sharing signal ground”. The signal coupling/decoupling circuit includes a comparator, a bi-directional switch and a variable voltage reference. The comparator senses the difference between the voltage on the common connection bus, the “common current sharing signal,” less an amount set by the variable voltage reference circuit, and the voltage on the module current sharing signal port, the “module current sharing signal”. If the module current sharing signal drops below the common current sharing signal, the comparator activates the bi-directional switch, disconnecting the module current sharing signal port from the common connection bus, allowing the remaining parallel connected modules to continue normal operation, thus providing a system that is tolerant of individual module faults.
U.S. Pat. No. 5,550,699 to Diaz issued Aug. 27, 1996 entitled “Hot plug tolerant ESD protection for an IC” discloses a bi-modal trigger circuit for ESD protection in an IC that is arranged to use the energy of the ESD event itself to trigger an SCR when VDD is absent and energy from VDD when VDD is present. This is accomplished by top and bottom inverters in series, and a trigger FET whose conduction triggers an SCR, and whose gate is driven by the voltage across the bottom inverter. The trigger threshold of the bi-modal trigger circuit may be raised above VDD when VDD is absent by the inclusion of a constant voltage drop inserted between the series connected top and bottom inverters that comprise the bi-modal trigger. This provides an offset voltage that must be overcome before a trigger FET can turn on and fire an SCR that does the actual ESD protection. The constant voltage drop may be produced by a series string of diode connected FET's. The threshold may also be increased by including a latch-connected feedback FET that shunts the gate of the trigger FET, thereby retarding the turn-on of the trigger FET until saturation in the feedback FET trips the latch. These two techniques can be used separately or in combination. When used in combination the number of diode connected FET's may be reduced to provide a constant voltage drop that is substantially less than the desired increase in the trigger voltage for the bi-modal trigger circuit.
U.S. Pat. No. 5,572,395 to Rasums, et al. issued Nov. 5, 1996 entitled “Circuit for controlling current in an adapter card” discloses a circuit embodied within an adapter card for hot-plugging with a card slot in a card slot coupled to a processor based system utilizes a biasing circuit for ensuring that the input voltage to the load of the adapter card is of a sufficient magnitude. The circuit also includes a FET/feedback circuit for opening and closing the circuit provided between the input voltage to the adapter card and the load. This FET/feedback circuit operates as a constant current source to charge the input capacitance of the load and converts to a switched mode when the load capacitance is fully charged. The biasing circuit controls the FET/feedback circuit so that it remains open during hot-plugging of the adapter card into the card slot to alleviate pin arching. A monitor/timer circuit prevents the FET/feedback circuit from operating in the constant-current mode for no longer than a predetermined amount of time. A latch circuit is provided to turn off the FET within the FET/feedback circuit upon sensing of a transient current through the load.
U.S. Pat. No. 5,944,827 to Shima et al. issued Aug. 31, 1999 entitled, “Power saving control system and method for use with serially connected electronic devices” discloses a system including a plurality of electronic devices connected together through a bus, which can realize reduction in power consumption while ensuring communications. When a bias voltage on an external bus is detected by a bias detecting circuit and a comparator, a bias voltage is output from a bias output terminal to the external bus enabling it. When a driver and receiver receive a PHY-SLEEP command through the external bus, the bias voltage output from the bias output terminal to the external bus is turned off, disabling it.
U.S. Pat. No. 6,333,643 to Kurooka, et al. issued Dec. 25, 2001 entitled, “Hotplug tolerant I/O Circuit” discloses a hotplug tolerant I/O circuit, which is incorporated in a first device, includes a voltage generator. In a hotplug mode, in which an input signal higher than the power supply voltage is applied from a second device to the first device while the power supply voltage is not applied to the first device, the voltage generator generates a control voltage from the input signal, and supplies it to a transistor in the hotplug tolerant I/O circuit.
U.S. Pat. No. 7,130,175 to Dietz et al. issued Oct. 31, 2006 entitled, “Monolithic integratable circuit arrangement for protection against a transient voltage” discloses protection of at least one or more terminals of an integrated circuit, such as a low- or high-side driver stage against transient or over-voltages by two pairs of diodes. A first pair of diodes includes a regular diode and a Zener-diode. A second pair of diodes also includes a regular diode and a Zener-diode. These diode pairs are looped into the respective circuit and cooperate with an n-channel MOSFET or a p-channel MOSFET to ostensibly provide over-voltage protection, particularly for transmitter/receiver circuits and databus systems such as in motor vehicles.
Despite these various approaches, the prior art neither teaches nor suggests effective apparatus or methods for effectively handling events, including more robust late-VG events, to prevent hotplug damage to a PHY chip or other such device. Accordingly, what is needed is an improved apparatus (and associated method of operation) with a response time fast enough to prevent hotplug damage to the serial port, yet at the same time robust enough to ground excessive voltage without becoming overstressed and failing, even in cases of shorts or near-shorts between outgoing power terminals and the signal pairs.
Such improved apparatus and methods would also ideally be substantially “automatic” (i.e., not require user intervention), and adaptable to a number of different form factors and applications.